Today, there are Very Large Scale Integrated (VLSI) circuits, herein referred to as chip(s), that have hundreds of millions of transistors with frequencies greater than 1 Gigahertz. In these chips there are many aspects of a design that have to be analyzed to verify that the design will function as intended. One aspect of this analysis is signal integrity. On VLSI chips there are many millions of interconnections between devices. Each of these interconnections has a device(s) that is changing the state, or the signal, on the interconnection, herein called a driver(s), and a device(s) that is reading the signal from the interconnection, herein called a receiver(s). Signal integrity can be explained as a measure of how distorted the signal is that arrives at the receiver versus what the driver intended to send to the receiver.
There are many interactions that can cause signal integrity to degrade. An assumption that is generally made in designing the devices that drive and receive the signals is that the supply voltage for all of the devices fluctuates. In the case when there is a high density of simultaneous witching circuits such as latches the power supply rail will collapse, resulting in chip malfunctions or performance degradation This power supply collapse is proportional to the area in which the devices reside. So, the higher the device density the greater the potential for the power supply to fluctuate.
One of the ways to counteract this power supply fluctuation is to add capacitance (decap) in high-frequency chip designs. Quiescent circuits also provide decoupling capability but the decoupling capacitor or decaps is specifically designed to provide a much higher capacitance density, usually 5×-10× greater than a quiet circuit. Although these decaps provide significant increase in the total on-chip voltage rail capacitance, the effectiveness of these elements are greatly diminished as a function of the distance from the active circuits. Therefore there is a need to analyze whether the decoupling capacitors placement throughout the chip is located in close proximity with sufficient quantity to simultaneous switching circuits such that voltage supply fluctuations is contained within design specifications. U.S. Pat. No. 6,323,050 “Method for Evaluating Decoupling Capacitor Placement for VLSI Chips”, Allan H. Dansky et al. has focused on custom chip designs such that lowest level entities are one of a kind macro circuits or group of basic circuit elements to make a function.